Aluminum Josephson junction microstructure and electrical properties modified by thermal annealing | Scientific Reports

Scientific Reports volume 14, Article number: 26066 (2024) Cite this article 331 Accesses Metrics details Reproducibility of Al/AlOx/Al Josephson junctions is a challenge for scaling up

Scientific Reports volume 14, Article number: 26066 (2024) Cite this article

331 Accesses

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Reproducibility of Al/AlOx/Al Josephson junctions is a challenge for scaling up superconducting quantum processors. The frequency uncertainty of the transmon qubits arising from the fabrication process is attributed to deviations in the Josephson junction microstructure and electrical properties. Here, we present a solution for this problem using the post-fabrication Josephson junction thermal annealing process. The developed thermal post-exposure method allows not only to increase the junction resistance by 175%, but also to decrease by 60% with a step of 10% in Rn, which opens up new possibilities for tuning the frequency of qubits. The resistance is shown to be strongly temperature dependent, and is weakly dependent on the holding time. The linear dimensions of the electrodes and the sidewalls contribution to the total JJ area also have a significant impact on the final resistance after annealing. Finally, a theoretical model of the structure modification in a tunnel barrier with changes in oxygen concentration gradient is proposed. The proposed thermal annealing approach can be used to form stable and reproducible tunnel barriers and scalable frequency trimming for widely used fixed-frequency transmon qubits.

Superconducting quantum circuits are promising platform for quantum computing1,2,3,4,5,6. In recent experiments, qubit circuits have approached the threshold for achieving quantum supremacy7. However, significant challenges still need to be addressed in order to develop fault-tolerant quantum processors. A qubit decoherence and frequency collisions are the most critical issues for scalable superconducting circuits8. A precise fabrication of the Josephson junctions (JJ) is necessary to provide the required frequency of fixed-frequency transmons9,10. Typical transmon frequencies deviation is 1–2%, which is 2–4 times worse than the best experimental results11,12. This becomes especially important for a scalable fabrication of superconducting circuits. Therefore, methods of post-fabrication tuning JJ to improve a frequencies qubit reproducibility have been widely developed recently. The laser annealing technique used for selectively trimming of individual qubit allow to high frequencies precision up to 0.3%11. Thermal annealing methods to adjust and stabilize post -fabricated the resistance of the tunnelling barrier (and correspondingly, transmon frequencies) have been explored previously13,14,15. This technique has a wide range of resistance increasing of 4 times, and leads to an increasing tunnel barrier quality, and consequence, qubit coherence improvement16.

In addition to frequency collisions, a major problem for scalability is the coupling of superconducting qubits with their environment, making them sensitive to uncontrolled sources of decoherence17,18. For example, coupling to the outside world occurs through electrical leads and to the device-level surroundings through direct electromagnetic interactions. Decoherence can be suppressed by filtering and shielding techniques19. At the device level, progress has been made by optimizing the circuit design operating the qubit at an optimal bias point or using special measurement techniques20,21,22,23. However, such approaches may not be effective when the decoherence sources originate within the material components forming the qubit. The amorphous nature of AlOx tunnelling barrier results in the inclusion of defects that can cause two-level systems (TLS’s) with decreasing qubit coherence. Solving this problem also involves thermal annealing. Changes in electrical characteristics occur because of the modification of the Josephson junction barrier structure (crystallization of amorphous AlOx). This also makes it possible to improve the coherence of superconducting circuits by reducing the density of TLS8.

In this paper, we introduce a post-fabrication tuning JJ method for a controlled changing of a normal resistance Rn. We demonstrate wide range of resistance tuning with an increase to 175% and a decrease to 60% for JJ areas of 0.01, 0.025 and 0.1 μm2. We observe a not standard behaviour of the JJ tunnel barrier at temperatures of 200 and 300 °C. Such annealing lead to a decreasing of the normal resistance. We show the resistance depends on a temperature and a holding time, and can decrease to 60% for a small junction area of 0.01 μm2. Our hypothesis is that some temperature exposure lead to reduce a normal resistance by the tunnel barrier thinner. The thin layer contains a smaller TLS density that need to improve the qubit coherence. We also believe our experimental results can helpful to understand the internal mechanisms of the tunnel barrier under thermal exposure. In general, the proposed technique allows to increase and decrease of the JJ normal resistance in a wide range and can be further improved with local JJ tuning techniques. Obtained results open up possibilities for the scalable high coherence quantum circuits.

For this study, we used high-resistivity silicon substrates (10,000 Ω·cm). Prior to base layer deposition, the substrate is cleaned in a Piranha solution at 80 °C, followed by dipping in a hydrofluoric bath24. 100 nm thick Al base layer is deposited using an ultra-high vacuum e-beam evaporation system. Pads were defined using direct-laser lithography and dry-etched in BCl3/Cl2 inductively coupled plasma. The Josephson junctions, described in this work, were fabricated using Niemeyer- Dolan technique25,26. This method has several advantages over the Manhattan junctions27,28. Smaller evaporation angles result in improved electrode surface roughness29. In addition, bridge technology is more suitable for the fabrication of large arrays of junctions, e.g., for parametric amplifiers30. The substrate is spin coated with a resist bilayer composed of an EL9 copolymer and chemically amplified resist CSAR 62. Layouts were generated and exposed using a 50 keV e-beam lithography system. Al/AlOx/Al junctions were shadow evaporated in deposition system. Resist lift-off was performed in N-methyl-2-pyrrolidone. Finally, we patterned and evaporated aluminum bandages using the same process as for junctions with in-situ Ar ion milling31. The chip topology contains a JJ array with areas of 0.01, 0.025 and 0.1 μm2 (60 JJs for each area). In addition, we varied the ratio of the top and bottom electrodes linear dimensions (30 JJs for each ratio of linear dimensions). The linear dimensions and contribution of the area sidewall are presented in Table 1. A total of 420 JJs inside 12\(\:\times\:\)12 mm2 area chip tested for each thermal annealing mode.

The quality and uniformity of the deposited electrodes were examined using scanning electron microscopy. To investigate the microstructure of Josephson junctions, lamellae were prepared and then examined using the facility of TEM, which is equipped with an X-ray Energy Dispersive Spectroscopy (EDS). The JJ room temperature resistance was individually measured using an automated probe station. The stylus profiler was used to measure the surface roughness of the bottom JJ electrode. Thermal annealing was performed in a rapid thermal process powerful multi-zone infrared lamp furnace. The substrate temperature was controlled using thermocouples. Annealing was performed in an argon atmosphere with varying temperature and holding time.

We investigate the influence of temperature (200, 300, 400, and 500 °C) and holding time at temperature (w/o holding time, 10 and 60 min) of thermal annealing on Rn tuning. The heating and cooling time are kept at 10 min and 60 min, respectively, for all experiments in this work. A typical process at 400 °C and 10 min holding time is shown in Fig. 1a. In addition, we determined the difference between room resistances before and after thermal annealing (Δ). Dependences Rn on the annealing temperature and holding time are shown in Fig. 1d–f.

Typical process of thermal annealing at 400 °C with 10 min heating time, 10 min holding time, and 60 min cooling time (a); SEM image of the fabricated junction used in this work with diagram of a single JJ (b); oxygen concentration gradient in the tunnel barrier at the Al/AlOx interface before and after thermal annealing (c); dependence of the change in the resistance value on the thermal annealing mode for JJ with area (above each mode indicated the coefficient of variation Rn): 0.010 μm2 (d), 0.025 μm2 (e), 0.100 μm2 (f).

The sensitivity of the junction resistance shift is characterised with respect to on the thermal annealing mode and the junction areas, allowing fine control of the junction resistance to meet specific frequency targets. The decrease in Rn reaches 60% at a mode of 400 °C and 10 min of holding time for a junction area of 0.01 μm2. Whereas an increase in Rn up to 175% is observed at a mode of 400 °C and 60 min for a junction area of 0.1 μm2. In all thermal annealing modes, a change in the СV(Rn) is observed. This may be caused by the polycrystalline structure of the aluminum bottom electrode. This makes the process less controllable, resulting in deviations for smaller junctions and higher СV(Rn) compared to junctions with larger areas. With thermal annealing at 500 °C, the JJ thin-film layer was destroyed and CV(Rn) increased up to 40% over the chip, negating the viability of utilizing temperatures surpassing 400 °C for junction thermal annealing. As a result of Josephson junction thermal annealing, we obtained both an increase and a decrease in the room temperature resistance. The increase in resistance is a typical result and has been obtained in many studies16,32,33. The decrease is an unexpected observation and can be theoretically described by the diffusion of oxygen atoms in the tunnel barrier. Figure 1c, shows the tunnelling barrier of the Josephson junction. As a result of the JJ aluminum electrode thermal oxidation, an oxygen concentration gradient is observed in the tunnel barrier35. Due to the thermal action and electric fields in JJ barrier, the oxygen concentration gradient decreases35. This reduces the effective thickness of tunnel barrier from h0 to hA, thereby decreasing resistance. An increase in resistance can be obtained by crystallizing the amorphous structure of aluminum oxide16,21,32,33,34. This result was noticed only in one mode of thermal annealing (400 °C and 60 min holding) for all JJ sizes. This is explained in the following way. Before reaching a certain temperature and holding time, the system does not have enough energy for the transition from an amorphous state to a crystalline state. This threshold is reached at 400 °C and holding times in the range of 10–60 min.

With an increase in the sidewall contribution (Table 1), differences in the resistance change were observed (Fig. 2a). More specifically, for sizes 150 × 170 nm2 (the sidewall contribution is 39%) and 230 × 110 nm2 (the sidewall contribution is 50%) with annealing mode 400 °C and holding time of 60 min, room resistance increased by 38% and 15%, respectively. To understand the physics of the process, lamellae cut from Josephson junction sites were investigated using TEM (Fig. 2b). To conduct chemical analysis, high-resolution EDS was applied to map the upper layer of tunnel barrier. TEM micrographs coupled with elemental maps of O and a crosssectional profile of oxygen atomic percentage confirmed the presence of oxygen concentration gradient in tunnel barrier. Instead of an abrupt change of oxygen content at the AlOx/Al interface, interfacial layers with a thickness of approximately 0.5 nm with oxygen deficiency are observed. A similar study was carried out for the sidewall of JJ, which had markedly high oxygen content in this region (Fig. 2e). A sidewall with an obviously thicker oxide layer is not initially involve in tunneling process, as can be seen from the initial room resistance for all Josephson junction sizes (Fig. 2a). However, annealing at 400 °C activates the mechanisms of structural changes in the tunnel barrier. The oxide thickness is equalized over the entire barrier area. Thus, at an annealing temperature of 400 °C and a holding time of 60 min, we observe a complete match between the resistance of the Josephson junction and the effective barrier area taking into account the sidewall contribution. This increases the JJ effective area involved in the tunneling process. As the contribution of the sidewalls to the Josephson junction area increases from 39 to 50%, the resulting area changes from 0.042 to 0.051 μm2, respectively. This difference in the JJ final area determines the difference in room resistance by 2.5 times for shapes 150 × 170 nm2 and 230 × 110 nm2 and the annealing mode at 400 °C and 60 min holding.

Dependence of the change in resistance on the thermal annealing mode for JJ with different contributions of the sidewall (junction area – 0.025 µm2) (a); TEM image of the AlOx layer (b); quantitative map of oxygen (atomic percentage) (c); cross-sectional line profile of the oxygen ratio from the marked area (zone I – centre) (d); cross-sectional line profile of oxygen ratio from the marked area (zone II – sidewall) (e).

.For the annealing mode of 200 °C without holding and 400 °C with 60 min holding time, the change in the root mean square roughness of the bottom electrode was estimated. Both modes change morphology of the thin film coatings. For annealing at 200 °C w/o holding did not give significant changes in roughness. In contrast, annealing at 400 °C with 60 min holding time increased the surface roughness of the bottom electrode by 4.4 Å. A change in the bottom electrode morphology affects the JJ effective area. A previous study showed that only 10% of the total barrier area is active in the tunnelling process36,37. AlOx thickness variations are primarily caused by grain boundary grooving in the bottom polycrystalline Al electrode. The tunnelling probability of charge carriers across the barrier is an exponential function of the barrier thickness. It has been shown that a 0.2 nm decrease in barrier thickness could result in one order of magnitude change in tunnelling current37. Thus, the thinnest region in the barrier may act as an active region or «hot spot» for tunnelling. Increasing the RMS surface roughness of the electrode may decrease the percentage of the area involved in tunneling. Thus, decreasing the effective area increases Rn.

Changing the resistance in both directions (increase and decrease) opens up new possibilities for the frequency detuning of superconducting qubits. The developed method of thermal annealing allows not only to increase the junction resistance by 175%, but also to decrease Rn by 60%. The tuning technique is capable of a step of 10% in Rn as the resistance decreases. LASIQ allows you to point-to-point increase in resistance, thereby lowering the qubits in frequency. Our method allows us to roughly reduce the resistance by raising the frequency value, and then locally tune them. After sorting Reference 38 is not cited in text. Please either cite it or delete this reference from the reference list."

To solve the problems of frequency collisions and decoherence of superconducting qubits, we performed a systematic study of Josephson junction thermal annealing technology. To achieve this, we fabricated a significant number of junctions and directly measured the change in their room temperature resistance depending on the thermal annealing mode. We achieved an Al/AlOx/Al junction Rn increase of 175% and a decrease of 60% with a step of 10% in Rn. The increase in JJ resistance is a typical result that can be obtained by crystallizing the amorphous structure of aluminum oxide and changing the bottom electrode morphology. We suppose the resistance reduction connect with an effective thickness decrasing due to the diffusion of atoms in the oxygen concentration gradient. Thermal annealing increases the effective junction area by equalizing the thickness of the tunnel barrier and incorporating the sidewalls into the tunneling process. The results obtained open up new possibilities for frequency tuning of qubits: raise or lower the frequencies of already fabricated qubits across the chip. The proposed method is compatible with technologies of local anneal Josephson junctions, and their combination will allow tuning of the qubit frequencies over a wide range for scalable superconducting processors.

The data that support the findings of this study are available within the article and from the corresponding author upon reasonable request.

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Samples were fabricated and studied at the BMSTU Nanofabrication Facility (FMN Laboratory, FMNS REC, ID 74300).

FMN Laboratory, Bauman Moscow State Technical University, Moscow, Russia, 105005

Nikita D. Korshakov, Dmitry O. Moskalev, Anastasia A. Soloveva, Daria A. Moskaleva, Evgeniy S. Lotkov, Artem R. Ibragimov, Margarita V. Androschuk, Ilya A. Ryzhikov, Yuri V. Panfilov & Ilya A. Rodionov

Dukhov Automatics Research Institute, VNIIA, Moscow, Russia, 127030

Nikita D. Korshakov, Dmitry O. Moskalev, Anastasia A. Soloveva, Daria A. Moskaleva, Evgeniy S. Lotkov & Ilya A. Rodionov

Institute of Theoretical and Applied Electrodynamics, Russian Academy of Science, Moscow, Russia, 125412

Ilya A. Ryzhikov

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I.R. (Ilya Rodionov), I.A.R. (Ilya Anatolevich Ryzhikov), D.O.M. conceptualized the ideas of the project. N.D.K., A.A.S. and M.V.A. fabricated experimental samples and discussed results. D.A.M. and A.R.I. performed morphology characterization. N.D.K. and E.S.L. conducted the process of thermal annealing of the experimental samples. N.D.K. and D.O.M. conducted the electrical characterization of the experimental samples. N.D.K., D.O.M., I.A.R. and I.R. analyzed the experimental data and discussed the results. N.D.K., D.O.M. and Y.V.P. prepared writing-original draft. I.R. reviewed and edited the manuscript. I.R. supervised the project. All authors analyzed the data and contributed to writing the manuscript.

Correspondence to Ilya A. Rodionov.

The authors declare no competing interests.

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Korshakov, N.D., Moskalev, D.O., Soloveva, A.A. et al. Aluminum Josephson junction microstructure and electrical properties modified by thermal annealing. Sci Rep 14, 26066 (2024). https://doi.org/10.1038/s41598-024-74071-7

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Received: 16 May 2024

Accepted: 23 September 2024

Published: 30 October 2024

DOI: https://doi.org/10.1038/s41598-024-74071-7

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Aluminum Josephson junction microstructure and electrical properties modified by thermal annealing | Scientific Reports